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YAO Jiangyu, WANG Yinshen, QIU Xiaolan, et al. Efficient FPGA acceleration technique for hierarchical detection of high-dynamic weak targets[J]. Journal of Radars, in press. doi: 10.12000/JR26057
Citation: YAO Jiangyu, WANG Yinshen, QIU Xiaolan, et al. Efficient FPGA acceleration technique for hierarchical detection of high-dynamic weak targets[J]. Journal of Radars, in press. doi: 10.12000/JR26057

Efficient FPGA Acceleration Technique for Hierarchical Detection of High-dynamic Weak Targets

DOI: 10.12000/JR26057 CSTR: 32380.14.JR26057
Funds:  The Strategic Priority Research Program of the Chinese Academy of Sciences (XDB0870000, XDB0870300, XDB0870301, XDB0870302)
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  • Corresponding author: QIU Xiaolan, qiuxl@aircas.ac.cn
  • Received Date: 2026-03-12
  • Rev Recd Date: 2026-05-11
  • Available Online: 2026-05-15
  • In space situational awareness systems, accurate detection of high-dynamic weak targets is critical. However, the rapid relative motion between the target and radar causes migration across range and Doppler cells. Moreover, the high computational complexity of traditional compensation algorithms hampers existing hardware platforms in meeting real-time processing demands. To address these challenges, we propose a hierarchical detection algorithm for highly dynamic weak targets paired with a corresponding field programmable gate array acceleration architecture. At the algorithmic level, we develop a cascaded processing strategy that leverages the short-term motion characteristics of the target and the parameter decoupling advantages of the Lv’s Distribution (LVD). This strategy combines coarse estimation through the reduced-dimension Radon-LVD (RLVD) with local fine-search compensation, effectively reducing computational complexity while preserving coherent integration gain. At the hardware level, an end-to-end real-time processing system is designed, centered around an 8-channel parallel RLVD computation kernel. Experimental results demonstrate that operating under a 200 MHz system clock, the system achieves real-time processing of 4-channel, single-frame 32 × 8192 echo data within an 8.41 ms full-pipeline latency. Core parameter estimation exhibits minor deviations compared to the floating-point model, with a maximum 3D positioning quantization deviation of 1.220 m. In addition, we validate the engineering feasibility of the proposed architecture in practical detection scenarios using real-measured data from a ground-based radar.

     

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